AMD Strix Halo: A Powerful Fusion of Zen 5 and RDNA 3+

AMD Strix Halo: A Powerful Fusion of Zen 5 and RDNA 3+

Chiplet Architecture

The Strix Halo APUs are built on a chiplet design, utilizing up to three dies: two CCDs (Core Complex Dies) and one GCD (Graphics Core Die). These chips boast up to 16 Zen 5 cores with 32 threads. Notably, they retain the same L1 and L2 cache structure, providing a maximum of 16 MB L2 cache. However, the L3 cache has been significantly increased to 32 MB per CCD, resulting in a potential total of 64 MB of L3 cache on the top-tier chips.

I/O Blocks and Connectivity

The GCD, the largest of the three dies, houses all the I/O blocks. It features an XDNA 2 AI NPU capable of delivering over 40 TOPs, 32 MB of Infinity Cache, and 256-bit LPDDR5X memory. Additionally, there might be Zen 5 LP (Low-Power) cores onboard this die. The GCD/IOD connects to the dual Zen 5 CCDs via the Infinity Fabric interconnect.

RDNA 3+ Graphics

On the iGPU side, the Strix Halo APUs retain the RDNA 3+ graphics architecture. They come equipped with 20 WGPs (Workgroup Processors) or 40 Compute units. To support these high-end iGPUs in a chiplet design, an additional 32 MB of MALL cache is onboard the IOD, eliminating bandwidth bottlenecks for the uber iGPU.

Memory and AI Capabilities

These APUs support up to LPDDR5x-8000 (256-bit) memory and feature an AI “XDNA 2” NPU capable of delivering over 70 TOPs. The Strix Halo APUs are centered around the latest FP11 platforms, offering TDPs of 70W (cTDP 55W) and peak ratings of up to 130W.

Display and Connectivity

Both the AMD Strix and Strix Halo APUs come with support for eDP (DP2.1 HBR3) and external DP (DP2.1 UHBR10), USBC Alt-DP (DP2.1 UHBR10), and USB4 Alt-DP (DP2.1 UHBR10). Strix Halo even features up to DP2.1 UHBR20 support.

In summary, the AMD Strix Halo APU represents an exciting leap forward, combining Zen 5 processing power with RDNA 3+ graphics muscle. Keep an eye out for its official announcement at Computex 2024! 🌟🔥