Intel’s “Skymont” E-core: A Double-Digit IPC Boost

Intel’s “Skymont” E-core: A Double-Digit IPC Boost

Amidst all the buzz surrounding Intel’s next-generation “Lion Cove” P-cores (which will power the upcoming “Lunar Lake” and “Arrow Lake” microarchitectures) as they compete with AMD’s “Zen 5,” it’s easy to overlook the equally exciting “Skymont” E-cores. These E-cores will feature not only in Intel’s upcoming microarchitectures but also as standalone cores in the energy-efficient “Twin Lake” processors.

Pictures from an Intel presentation, possibly intended for PC OEMs, were leaked online. Although we only have thumbnails of the slides, we’ve managed to glean some exciting details. So, let’s break it down:

1. IPC Gain: The “Skymont” E-core is expected to deliver a double-digit IPC gain over the current “Crestmont” E-core, which itself boasted a roughly 4% IPC improvement over the “Gracemont” E-cores found in the “Raptor Lake” and “Alder Lake” microarchitectures.

2. Matching the Best: With this IPC boost, the “Skymont” E-core is projected to match the IPC performance of the formidable “Sunny Cove” or “Willow Cove” P-cores. These cores powered the “Ice Lake” and “Tiger Lake” microarchitectures, respectively, and were already within the 90th percentile of AMD’s “Zen 3” core in terms of IPC.

3. Under the Hood: How is Intel achieving this impressive IPC gain? Let’s take a peek:

   • Improved Branch Prediction Unit: The “Skymont” E-core benefits from an enhanced branch prediction unit, which helps improve instruction flow and execution.
   • Wider Decode Unit: Compared to the 6-wide Decode unit of “Crestmont,” the “Skymont” E-core boasts a broader 9-wide Decode unit. This allows for more efficient instruction decoding.
   • Expanded Integer ALU: The “Skymont” E-core features an 8-wide integer ALU (Arithmetic Logic Unit), doubling the number of integer execution units compared to its predecessor.
   • Dependency Optimization: Intel has optimized dependencies in the out-of-order execution engine, reducing stalls and improving overall efficiency.
   • Deeper Queuing: The engine now supports deeper queuing, allowing for better utilization of execution resources.

4. Clustered L2 Cache: While details are scarce, it’s likely that the E-cores will still be organized into clusters that share an L2 cache among a certain number of cores.

In summary, the “Skymont” E-core promises a significant leap in IPC performance, positioning it as a worthy competitor to AMD’s best. As we eagerly await its official release, tech enthusiasts can look forward to exciting advancements in Intel’s microarchitectures.

Stay tuned! 🚀