RISC-V Day Tokyo 2025: Advancing Open-Source Semiconductor Innovation

RISC-V Day Tokyo 2025 Spring, Japan's largest RISC-V event, will bring together engineers, researchers, industry leaders, and enthusiasts to explore the latest advancements in open-source semiconductor technology. Scheduled for Thursday, February 27, 2025, from 9:00 to 18:00 JST (UTC+9), the conference will be held at the Ito International Research Center, The University of Tokyo. This article highlights the event's significance, key features, and its role in shaping the future of computing.

The Rise of RISC-V and Its Ecosystem

RISC-V is an open-standard instruction set architecture (ISA) developed in 2010 at UC Berkeley under Professor Krste Asanović. Unlike proprietary ISAs like Arm, RISC-V is freely available, allowing developers and companies to innovate without licensing fees. Its flexibility and modularity have driven rapid adoption across industries, including IoT, AI, high-performance computing (HPC), and automotive applications.

Japan's RISC-V community is thriving, with active contributions from academia, industry, and research institutions. RISC-V Day Tokyo serves as a vital platform for collaboration, innovation, and showcasing cutting-edge technologies.

Event Overview: RISC-V Day Tokyo 2025 Spring

Organized by the RISC-V Association and supported by Software Hardware Consulting, RISC-V Day Tokyo 2025 Spring is part of a series of RISC-V events in Japan. It aims to connect key people, engineers, and technologies while fostering business opportunities and knowledge exchange.

Key Details:

Date and Time: February 27, 2025, 9:00-18:00 JST (UTC+9)
Venue: Ito International Research Center, The University of Tokyo, Bunkyo-ku, Tokyo
Registration: Open now at riscv.or.jp
Poster Session Deadline: Abstract submissions due by January 20, 2025
Language: Primarily Japanese, with select sessions in English (TBD)

Event Highlights

RISC-V Day Tokyo 2025 offers a range of activities tailored to diverse interests. Here are the key highlights:

1. RISC-V Solutions

This segment will feature presentations and demos of RISC-V-based solutions, including:

Embedded systems and IoT devices
AI and machine learning accelerators
High-performance computing (HPC)
Automotive and industrial applications

Attendees can explore live demonstrations of RISC-V chips, development boards, and software tools. Companies like SiFive, a leading RISC-V IP provider, are expected to participate, based on past events and social media posts (subject to confirmation).

2. Special Event: Japan's Semiconductor Strategy 2025 & RISC-V | AI

A dedicated session will focus on Japan's semiconductor strategy for 2025, emphasizing RISC-V's role in AI and chip design. Topics include:

Strengthening Japan's semiconductor industry
Collaboration between academia, industry, and government
RISC-V's impact on AI-specific processors

This session aligns with Japan's efforts to revitalize its semiconductor sector amid global supply chain challenges. Related publications, such as Japan's Semiconductor Strategy 2024+1/2-NVIDIA and AI Chip Companies (available from November 19, 2024), will provide additional context.

3. RISC-V Lunch Party

A networking lunch will allow attendees to connect, discuss collaborations, and share insights in an informal setting, fostering relationships within the RISC-V community.

4. Poster Session

The poster session offers researchers and engineers a platform to present their work on topics such as:

Novel RISC-V core designs
Security enhancements (e.g., CHERI)
Open-source silicon initiatives
Performance optimization for RISC-V processors

Abstract submissions are due by January 20, 2025, and accepted posters will be displayed during the event, providing visibility for early-career researchers and students.

5. Exhibitions and Demos

Exhibition booths will showcase RISC-V-related products and technologies. Past events have featured unique RISC-V chips, such as those designed with Chisel, and VGA controllers. Exhibitors for 2025 are subject to change, but a diverse range of innovations is expected.

Why RISC-V Day Tokyo 2025 Matters

RISC-V Day Tokyo 2025 is a catalyst for innovation and collaboration in the global RISC-V ecosystem. Here's why it stands out:

1. Driving Open-Source Innovation

RISC-V's open-standard nature democratizes processor design, enabling companies to develop custom chips. The event accelerates this process by fostering knowledge sharing and collaboration, addressing challenges like power consumption in data centers and IoT security.

2. Addressing Japan's Semiconductor Challenges

Japan's semiconductor industry faces declining market share and supply chain disruptions. RISC-V offers a pathway to revitalize the sector by enabling rapid prototyping and reducing costs. The special event on Japan's semiconductor strategy will explore these issues, drawing on initiatives like Rapidus.

3. Fostering Global Collaboration

While rooted in Japan, the event attracts global participants, encouraging cross-border partnerships and best practices. The RISC-V Association's ties to RISC-V International amplify its impact.

4. Empowering Engineers and Researchers

The conference provides engineers and researchers with opportunities to learn from industry leaders, explore technologies, and contribute to RISC-V's development. The poster session is particularly valuable for emerging talent.

Post-Event Resources

Post-conference, presentation videos and materials will be available on riscv.or.jp, ensuring accessibility and continued engagement.

Conclusion

RISC-V Day Tokyo 2025 Spring is a pivotal event for the RISC-V community, offering insights, collaboration, and innovation. Whether you're an engineer, researcher, or business leader, join the RISC-V revolution on February 27, 2025, at the University of Tokyo. Register at riscv.or.jp and be part of shaping the future of computing.

Note: Exhibitors, speakers, and content are subject to change. Check the official website for updates.