Huawei’s 910D Chiplet Design: A Game-Changer in Semiconductor Innovation

Introduction: Huawei’s Bold Move in Chiplet Technology

In a recent patent filing that has sent ripples through the tech world, Huawei has unveiled its ambitious 910D quad-chiplet design. This innovative approach, detailed in a post by Jukan Choi on X (dated June 22, 2025), suggests that Huawei is not only mimicking NVIDIA’s quad-die Rubin Ultra but also pushing the boundaries of advanced packaging technologies. This development is particularly significant given the U.S. sanctions that have restricted China’s access to cutting-edge EUV lithography machines from ASML. Let’s dive into the details and implications of this breakthrough.

The Chiplet Revolution: Overcoming Manufacturing Challenges

Chiplets represent a paradigm shift in semiconductor design, breaking down the traditional monolithic System-on-Chip (SoC) into smaller, specialized dies assembled into a System-in-Package (SiP) through heterogeneous integration. According to Choi’s analysis, this approach addresses a critical manufacturing challenge: as die sizes increase, yield drops due to defects, reducing profitability. With China limited to DUV (Deep Ultraviolet) processes (54 steps vs. 28 with EUV), the yield for 7nm chips could fall by 23-41% (calculated as 0.99^26 ≈ 77% and 0.98^26 ≈ 59%).

This yield loss has driven Huawei to embrace chiplets, a strategy that optimizes smaller dies and leverages advanced packaging to compensate for the lack of EUV. The 910D’s potential 4,020 mm² footprint, including 1,360 mm² of HBM (High Bandwidth Memory) as per TrendForce data, positions it as a formidable contender in the AI processor market.

China’s Technological Counterattack

Despite sanctions, China is making strides in alternative technologies. Choi highlights Huawei’s prowess in hybrid bonding, where YMTC holds patent parity with TSMC, and even licenses technology to Samsung and Hynix. This expertise is crucial for chiplet integration, allowing Huawei to integrate consumer products ahead of Western competitors like Samsung and Apple, who are targeting 2026-2027 for similar adoption.

Additionally, BOE’s planned entry into glass interposer and substrate production by late 2025 (per Tom’s Hardware) could further alleviate the EUV bottleneck. This collective effort—spanning YMTC, SiCarrier, and BOE—underscores Choi’s bold claim: “Huawei is China, and China is Huawei.”

Performance vs. Power: The Trade-Off

While the 910D promises impressive performance, concerns about power consumption linger. Choi acknowledges that combining multiple chiplets increases energy use, though he suggests potential mitigations exist. The trade-off between performance and efficiency will be critical, especially as Huawei aims to rival NVIDIA’s AI GPUs. Data from the X thread and web sources indicate that interconnection bandwidth (e.g., 540GB/s in the 910C) and interposer design will play key roles in determining the 910D’s success.

Implications for the Global Semiconductor Race

Huawei’s 910D could signal a turning point, forcing Western firms to accelerate their chiplet strategies. The patent’s resemblance to NVIDIA’s Rubin Ultra suggests a direct challenge, while China’s focus on glass substrates and hybrid bonding may level the playing field. However, as one X user noted, China’s semiconductor industry remains “handicapped” compared to its football team’s competitiveness, reflecting the ongoing impact of sanctions.

For tech enthusiasts and industry watchers, keeping an eye on Huawei’s next moves will be essential. The 910D is more than a chip—it’s a symbol of resilience and innovation under pressure.

Conclusion

As of June 23, 2025, Huawei’s 910D chiplet design stands as a testament to China’s ability to adapt and innovate amidst adversity. With advanced packaging, hybrid bonding, and emerging glass interposer technologies, Huawei is not just catching up—it’s setting a new pace. Stay tuned for further developments in this evolving semiconductor saga!