Intel’s bLLC in Nova Lake: Flat Cache vs. AMD’s 3D V-Cache
Wednesday, August 06, 2025Intel’s bLLC in Nova Lake: Flat Cache vs. AMD’s 3D V-Cache
Discover how Intel’s Big Last Level Cache (bLLC) in Nova Lake compares to AMD’s 3D V-Cache. Learn about flat cache architecture, gaming performance, and AI potential.
Introduction
Intel’s Nova Lake CPUs are set to introduce bLLC (Big Last Level Cache)—a new approach to cache design that could challenge AMD’s 3D V-Cache dominance. Instead of stacking cache vertically, Intel spreads it flat across the die. This change could have major implications for gaming, AI, and thermal efficiency.
What Is bLLC?
- Up to 144MB of L3 cache per tile
- Designed for gaming, AI inference, and multitasking
- A flat layout that avoids the complexity of stacked cache
Nova Lake Core Configurations
| Model | P-Cores | E-Cores | LP E-Cores | Cache | TDP |
|---|---|---|---|---|---|
| Ultra 9 | 8 | 16 | 4 | 144MB | 125W |
| Ultra 7 | 8 | 12 | 4 | 144MB | 125W |
Intel vs. AMD: Cache Architecture Comparison
| Feature | Intel bLLC (Flat) | AMD 3D V-Cache (Stacked) |
|---|---|---|
| Cache Layout | Flat / 2.5D | Vertical stacking |
| Thermal Efficiency | Easier to cool | Requires advanced cooling |
| Voltage Constraints | Fewer limitations | Sensitive to voltage |
| Manufacturing | Simpler | More complex |
| Latency | Lower potential latency | May introduce latency |
Performance Expectations
- 60% multi-threaded uplift over Arrow Lake
- Better RAM independence
- Improved AI inference for local models
Platform Changes
- New LGA 1954 socket
- Support for higher power envelopes
- Potential for AI acceleration and advanced I/O
Conclusion
Intel’s bLLC is a bold move in CPU design. By avoiding stacked cache, it offers better thermal efficiency and scalability. Nova Lake could be a game-changer for gamers and AI developers alike.
Tags: Intel Nova Lake, bLLC, CPU Cache, AMD 3D V-Cache, Gaming Performance, AI Inference, CPU Architecture