Intel’s bLLC: A Smart Cache Strategy for Nova Lake-S

Intel’s upcoming Nova Lake-S architecture is generating significant attention—not because of a radical core redesign, but thanks to a clever and practical cache expansion technology: bLLC, or Big Last Level Cache. This innovation is Intel’s strategic answer to AMD’s 3D V-Cache, but instead of stacking cache vertically using Through-Silicon Vias (TSVs), bLLC is an on-die, planar cache design. It promises serious performance gains while avoiding the manufacturing complexity and expense of TSV stacking.

Let’s explore what bLLC is, why it matters for performance, and how it fits into Intel’s roadmap.

What Is bLLC?

bLLC (Big Last Level Cache) represents a significant increase in the L3 cache capacity on Intel’s upcoming Nova Lake-S desktop processors, expected in late 2026. Unlike AMD’s 3D V-Cache—which vertically stacks additional cache atop the CPU die—bLLC places a large L3 cache horizontally and directly on the die, specifically positioned in the center of the ring bus architecture.

Key Features:

On-die planar L3 cache (no TSV stacking)
Not a separate new cache level (no L4 cache)
Unlike the canceled Adamantine cache project, bLLC integrates into central die space
Efficient placement utilizes previously unused central die area

This approach permits Intel to greatly expand cache capacity without significantly increasing die complexity or manufacturing costs.

Why Intel’s bLLC Design Makes Engineering Sense

Intel’s bLLC strategy rests on several practical advantages:

Central Placement Reduces Latency: By positioning the cache centrally on the ring bus, all cores enjoy roughly equal and fast access, boosting performance in cache-sensitive workloads.
Simpler and More Cost-Effective Than TSV Stacking: Avoiding the complex and expensive TSV stacking technique used by AMD’s 3D V-Cache improves manufacturing yields and lowers costs.
Makes Good Use of Die Space: The central die area usually contains unused or underutilized space. Intel leverages this to add large L3 cache slices without bloating die size.

Performance Implications

Leaked data suggests that Nova Lake-S CPUs leveraging bLLC could deliver a 30–45% gaming performance uplift compared to Intel’s 2024 Arrow Lake platform—an impressive gain given that the core architecture changes are moderate.

Larger L3 caches reduce the frequency of slower DRAM accesses by holding more data closer to the CPU cores, which benefits modern games and AI workloads that are increasingly cache sensitive—resulting in smoother frame rates and accelerated compute tasks.

What’s Next: Moving Toward eLLC and Beyond

bLLC serves as a cost-effective stopgap, but Intel is also working on eLLC (Enhanced Last Level Cache)—a TSV-stacked cache approach akin to AMD’s 3D V-Cache.

Roadmap Highlights:

Nova Lake-S (2026): Utilizes bLLC only—excluding eLLC to control costs.
Titan Lake (Approx. 2028): Expected to combine bLLC and eLLC for peak cache density and performance.
Intel may innovate by stacking cache beneath the CPU die, potentially opposing AMD’s cache stacking methodology.

This layered cache roadmap aims to keep Intel competitive in gaming and AI workloads for years to come.

Why Nova Lake-S Skips eLLC

According to leaker Moore’s Law Is Dead (MLID), Intel excludes eLLC from Nova Lake-S because TSV stacking adds considerable complexity and manufacturing expense. Intel reserves eLLC technology for its future premium platforms where the cost premium is more justified.

bLLC, meanwhile, provides a practical cache size boost that allows Intel to close critical performance gaps with AMD’s 3D caching techniques without exorbitant manufacturing costs.

Final Thoughts

Intel's bLLC is a masterclass in pragmatic engineering: expanding cache capacity significantly while avoiding the complexity and risks of TSV stacking. Though less flashy than AMD’s 3D V-Cache, bLLC is a scalable and cost-effective solution that lays groundwork for future innovations like eLLC.

As cache size increasingly dictates CPU competitiveness—especially in gaming and AI workloads—Intel’s layered cache strategy could prove pivotal in its comeback, supporting both gamers and creators with meaningful performance gains over multiple CPU generations.

At a Glance

Launch: Late 2026 (Nova Lake-S)
Flagship Cache: 288MB bLLC L3 (two 144MB planar caches)
Process Node: TSMC N2P (flagship); Intel 18A for entry SKUs
Gaming Uplift: +30–45% vs Arrow Lake (bLLC models)
Socket: New LGA 1954, planned for 4 CPU generations