As part of its structural reorganization, Intel Corporation established a dedicated Central Engineering Group led by Srinivasan (Srini) Iyengar, Senior Vice President and Intel Fellow. Iyengar joined Intel after leading global silicon engineering at Electronic Design Automation (EDA) giant Cadence Design Systems.

Iyengar’s group consolidates horizontal engineering functions across Intel while spearheading a custom silicon business unit designed to co-develop semi-custom ASICs with hyperscale cloud partners.

Deep Dive: Srini Iyengar’s Technical Background

Iyengar brings deep expertise in automated chip design tools, IP integration, and custom ASIC methodologies:

• Cadence Global Engineering Lead: Managed advanced physical design, signoff, and design-for-manufacturability (DFM) flows across leading-edge node geometries.
• Hyperscale Co-Design: Worked directly with top-tier cloud providers to optimize custom silicon chips for specific AI, storage, and networking workloads.
• Intel Fellow Distinction: Holds the prestigious title of Intel Fellow, reflecting top-tier technical leadership within the company.

Strategic Importance of Central Engineering & Custom Silicon

1. Capturing the Custom ASIC Market

Hyperscale cloud providers increasingly desire custom accelerators alongside general-purpose CPUs. Under Iyengar's leadership, the Central Engineering Group allows external partners to combine their proprietary IP blocks with Intel’s compute tiles, I/O interfaces, and packaging technologies.

2. Unifying Horizontal IP Across Intel

Centralizing core design functions—such as PHY blocks, memory controllers, power management, and test validation—streamlines product execution across Intel's client, data center, and foundry divisions.

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