Intel Foundry White Paper: A 5 kW AI GPU Loses 4829 W Before It Computes

By Indie Kings | October 17, 2026

Updated October 17, 2026: Intel Foundry published a nine-page white paper in August 2026 arguing that power delivery, not transistor performance alone, is becoming a limiter on AI data center chips, and laying out its own menu of fixes. Its sharpest number: at 5,000 W of SoC power, a board draws 8,301 W of which only 3,472 W ends up as useful compute, per the paper's Figure 2.

Why Intel Foundry Is Now Selling Power Delivery

The document, "Driving Power Delivery Innovations for the AI Data Center Era," opens from Intel Foundry rather than Intel the PC company. It carries three authors: Kaladhar Radhakrishnan, a Distinguished Engineer in Semiconductor Technology; Vishal Javvaji, a Process Integration Manager; and Nicolas Butzen, a Principal Engineer. Its executive summary states plainly that "power delivery has become a significant limiter for performance scaling in modern data center chips," and that incremental improvements alone are no longer sufficient as rising current compounds resistive losses and voltage droop across the power delivery network, or PDN.

The paper cites Figure 1, a chart of data center accelerator power scaling with a series of NVIDIA accelerators from A100 through Rubin Ultra, Intel Gaudi 2 and Gaudi 3, and AMD MI300X, MI350X and MI455X, captioned as based on Intel Foundry analysis of publicly available information as of August 2026. Per the paper, modern integration levels now require package currents in the multi-kiloamp range at low supply voltages, and stacked-die multi-chip architectures make it worse by raising effective current density, routing congestion and reliability pressure.

The strategic point sits in the framing. A foundry that sells power delivery technology as a product is telling silicon and system architects that the wiring, the capacitors and the voltage regulators are now design-critical, not plumbing. Figure 2 is the argument for why that shift is happening now.

Image: Data center server racks, illustrative photo. Credit: Tony Webster, Wikimedia Commons, CC BY 2.0.

The Figure 2 Math: 8,301 W In, 3,472 W Useful

Figure 2, captioned "Degradation of power delivery network (PDN) efficiency at higher power levels," builds two bar diagrams side by side. The left one models a 1 kW GPU. The right one models a 5 kW GPU, which per the paper's chart is the territory of accelerators like NVIDIA's Rubin generation. These are the paper's own worked example, and every number below comes from its labels.

Read the right-hand column slowly. The board pulls 8,301 W into the power delivery chain for a nominal 5,000 W SoC. Converting from the motherboard voltage regulators (MBVRs) burns 1,079 W, shipping current across the distribution path burns 2,222 W in I2R losses, and the voltage guard band held against droop wastes another 1,528 W inside the SoC allowance. That leaves 3,472 W of useful power: less than 42 percent of everything the board drew, dividing the paper's own label values.

The superlinear regression is the point. Scaling the same paper's example from 1 kW to 5 kW, a fivefold power step, I2R losses grow 25-fold from 89 W to 2,222 W, droop waste grows nearly ninefold from 174 W to 1,528 W, and the wasted droop share of nominal SoC power rises from 17.4 percent to 30.6 percent. Compute the fractions from the labels and the board's end-to-end efficiency falls from roughly 66 percent to roughly 42 percent, which is why the paper calls for higher voltages and regulators moved closer to the load rather than another round of incremental PDN tuning.

From 10 kW Racks Toward 1 MW

The same scaling shows up one level up. Per the paper, traditional data center racks are designed for approximately 10 to 20 kW and rely almost exclusively on air cooling, while modern AI racks already exceed 100 kW and have largely moved to liquid cooling. Industry roadmaps cited in the paper project rack power approaching 1 MW by the latter part of the decade.

Intel Foundry reached for an external anchor to size the stakes: per a June 2026 estimate from Lawrence Berkeley National Laboratory cited in the paper, U.S. data centers could account for 11.8 percent of total U.S. electricity consumption by 2030, in a range of 9.5 to 15.3 percent depending on AI deployment assumptions. That is an upward revision from the same laboratory's 2024 report, which per the paper projected 6.7 to 12.0 percent by 2028.

Inside the rack, the paper notes a squeeze: denser racks leave less volume for power conversion and distribution while efficiency requirements tighten across the whole chain. That is the context in which a foundry starts shipping power delivery features alongside transistors.

PowerVia: Backside Power Delivery on Intel 18A

PowerVia, introduced on the Intel 18A node, reroutes primary power to the backside of the die so power routing and frontside signal interconnects stop competing for the same metal layers. Per the paper, this enables a significant reduction in on-die IR drop, frees frontside routing for signals, and improves standard cell utilization. In conventional frontside designs, the paper argues, every layer added to support signal density also forces current through more vertical interconnects and raises the effective resistance of the power path.

The paper also names two successors: PowerVia is described as the foundation for Power Boost on Intel 18A-P, a dual-contact architecture the paper says delivers over 10% higher frequency at matched capacitance, and PowerDirect is described as the second generation of Intel Foundry's backside power technology, planned for the Intel 14A node with additional area efficiencies. The paper is candid that realizing the backside benefits requires close co-optimization across process integration, thermal management and architecture.

Omni MIM, eMIM-T and eDTC: The Capacitor Stack

Decoupling capacitors are the paper's second pillar. Intel, per the document, was the first to introduce metal-insulator-metal (MIM) capacitors into high-volume logic technologies, and Omni MIM is its latest generation on-die MIM capacitor. Instead of adding electrode layers, Omni MIM extends the capacitor structure into the third dimension using vertical trenches in the inter-layer dielectric, which per the paper substantially increases capacitance density while staying close to the active circuitry.

Because on-die MIM charge storage is finite, the package has to carry the next stages of decoupling, and the paper says high-density accelerator packages have nearly no room left for discrete ceramic capacitors: the topside is full of compute and memory dies and the landside is dense with ball grid array connections for power and I/O. Two technologies fill that gap. The proprietary eMIM-T capacitor integrates multiple layers of high-density MIM capacitors inside the package build-up layers, connected through TSVs so it provides high-frequency decoupling without eating silicon area. Embedded deep trench capacitors (eDTC) sit inside the package core as another decoupling stage aimed at low- to mid-frequency needs, maximizing total in-package capacitance.

EMIB-T: Power Through the Bridge

EMIB, Intel Foundry's embedded bridge technology in volume since 2017, joins dies without a full silicon interposer. The paper flags a power problem as current density climbs with interfaces like HBM4 and next-generation UCIe: with traditional EMIB, power routes around the bridge structure, which per the paper increases path resistance and can create current crowding at edge bumps, raising both efficiency and reliability concerns.

The newer EMIB-T architecture puts TSVs directly inside the bridge, giving current a vertical path through the bridge rather than around it, which per the paper reduces resistive losses and distributes current more evenly across the bump array while easing edge bump reliability risk. EMIB-T also integrates MIM capacitors inside the bridge structure for local suppression of AC noise on high-speed I/O power rails. The paper's Figure 6 compares "EMIB: Current Architecture" against "EMIB-T: New Architecture" and decorates the chart with marker labels including 100% and 50% beside the words Bandwidth, Power and Noise; the body text itself makes no percentage improvement claims for EMIB-T, so the labels are best treated as the paper's directional before-and-after framing rather than audited results.

Integrated Voltage Regulators: FIVR and CoaxMIL

The voltage regulation arc is Intel's longest-running case study in the paper. Intel states it was the first to deploy integrated voltage regulators (IVRs) in high volume manufacturing over a decade ago. The original fully integrated voltage regulator (FIVR) put power switches, controller and output MIM capacitors directly on the processor die, using air core inductors in the package for energy storage.

Higher current densities degraded that approach, per the paper, because smaller air core inductor footprints hurt inductor quality and conversion efficiency. Intel's answer was CoaxMIL, a magnetic inductor solution first deployed on 4th Gen Intel Xeon Scalable processors, which reduced inductor footprint while improving power conversion efficiency. Newer CoaxMIL generations, per the paper, have shipped across subsequent Intel Xeon processor families and add coupled-inductor configurations that sharpen transient response and shrink footprint further. The paper's spotlight box explains the physics: motherboard regulators must switch slowly at 12 V and so need large inductors, while IVRs switch at much higher frequencies and so fit higher current density into far less area.

C2VR: The Capacitor-Only Voltage Regulator Chiplet

The continuous capacitive voltage regulator (C2VR) is the paper's headline component. It is a voltage regulator chiplet that uses high-density MIM capacitors integrated on the chiplet itself instead of inductors, converting an input of up to 2.4 V down to typical core-domain voltages. Per the paper, it offers more than 90% efficiency and 10 A/mm2 on a single piece of silicon, and can increase output current almost instantaneously, showing minimal voltage droop during high di/dt transients.

Integration flexibility is the rest of the pitch. The C2VR is scalable to multi-kiloamp current levels, supports placement on either the die side or the landside of the package, and can be thinned to less than 100 um while keeping full functionality. That thin profile lets input power arrive through backside TSVs, so the regulator can be embedded within package build-up layers or incorporated directly into the base die of stacked-die architectures, underneath the compute die. The paper walks through why the alternative landside IVR placement, while a practical near-term step, runs into electrical, thermo-mechanical and BGA resource limits at higher current densities.

The Foundry Menu

The most quotable strategic line in the document is its own disclaimer of dogma: "This paper does not advocate for a single, optimized power delivery solution." Intel Foundry instead pitches a toolkit: backside power delivery for on-die IR drop, a capacitor ladder from die to package, a bridge with power integrated into it, and regulator chiplets that scale from landside placement to embedded base-die integration. The paper's closing section says different applications, package architectures and power levels demand different combinations.

One honesty note belongs here: this is Intel Foundry documenting its own portfolio in its own white paper, so figures such as the C2VR's more than 90% efficiency and 10 A/mm2 density are Intel-reported, and the document itself carries Intel's standard disclaimer that performance varies by use and configuration. It is still, per our scoping, the most complete public worked example of where AI board power actually goes, and the competitor named in its charts, NVIDIA, is not the subject of its technology sections.

FAQ

What is the Intel Foundry power delivery white paper?
"Driving Power Delivery Innovations for the AI Data Center Era," a nine-page Intel Foundry white paper published in August 2026 by authors including Distinguished Engineer Kaladhar Radhakrishnan and Principal Engineer Nicolas Butzen. It surveys Intel Foundry's power delivery portfolio for AI and HPC chips.

How much power does a 5 kW GPU waste, per the white paper?
In the paper's Figure 2 example, the board draws 8,301 W for a 5,000 W SoC: 1,079 W is lost in the motherboard voltage regulators, 2,222 W in I2R distribution losses, and 1,528 W is droop guard band waste, leaving 3,472 W of useful power.

What does PowerVia do?
PowerVia, introduced on Intel 18A, moves primary power routing to the backside of the die so it no longer competes with signal routing on the frontside. Per the paper, this significantly reduces on-die IR drop and frees frontside routing resources for signals.

How efficient is Intel's C2VR regulator chiplet?
Per the paper, the C2VR is a fully capacitive regulator chiplet converting up to 2.4 V input that offers more than 90% efficiency and 10 A/mm2 on a single piece of silicon, and it can be thinned below 100 um for die-side or embedded placement. Note these are Intel-reported figures.

What changed between EMIB and EMIB-T?
Per the paper, EMIB-T embeds TSVs inside the silicon bridge so current flows through the bridge rather than around it, reducing resistance and edge bump current crowding, and adds MIM capacitors inside the bridge to suppress AC noise on I/O power rails.

Does the paper commit Intel Foundry to one power delivery approach?
No. The paper states it "does not advocate for a single, optimized power delivery solution" and presents a menu of complementary technologies for architects to combine by requirements.

Our Take

We think the most revealing number in this paper is not the 5 kW diagram but the trajectory: per Intel's own Figure 2, I2R losses grew 25-fold while the power grew fivefold, which means board efficiency quietly halves as accelerators scale. A foundry writing a glossary-grade document on capacitors and regulator chiplets, with a portfolio menu instead of a roadmap, reads as a bet that power delivery becomes a foundry selection criterion for 2027 and 2028 designs. We would like independent reproduction of the C2VR efficiency figures before treating that number as settled.

Bottom Line

Intel Foundry's August 2026 white paper makes the case that power delivery is now the limiter on AI data center chips, and its own Figure 2 shows why: on a 5 kW GPU, 8,301 W enters the board and only 3,472 W reaches useful compute, with the wasted droop guard alone consuming 30.6% of nominal SoC power. Its response is a portfolio, PowerVia backside power, the Omni MIM, eMIM-T and eDTC capacitor stack, EMIB-T with in-bridge TSVs, CoaxMIL inductors and the C2VR regulator chiplet, offered selectively rather than as a single mandate.

Sources

Driving Power Delivery Innovations for the AI Data Center Era, Intel Foundry white paper