Strategic Talent Migration: MediaTek Recruits Former Intel Packaging Chief Navid Shahriari to Accelerate AI ASIC Push
Strategic Talent Migration: MediaTek Recruits Former Intel Packaging Chief Navid Shahriari to Accelerate AI ASIC Push
An architectural review of MediaTek’s high-profile hire of 37-year Intel veteran Navid Shahriari as Senior Vice President, analyzing its dual CoWoS-EMIB packaging strategy for hyperscale AI accelerators.
As custom application-specific integrated circuits (ASICs) for artificial intelligence become the dominant growth engine for fabless chip designers, advanced packaging has eclipsed raw transistor scaling as the primary competitive bottleneck. Marking a monumental shift in executive talent migration, MediaTek has officially appointed former Intel senior executive Navid Shahriari as Senior Vice President.
Bringing 37 years of deep semiconductor engineering, data center design, and packaging leadership from Intel, Shahriari will oversee MediaTek’s advanced process platforms, design-technology co-optimization (DTCO), advanced testing, and packaging operations. Coming on the heels of MediaTek bringing in former TSMC R&D Vice President Douglas Yu as an advisor, this dual-veteran strategy positions MediaTek to aggressively scale its multi-billion-dollar AI data center business.
1. Engineering Leadership and Scope of Responsibility
Reporting directly to MediaTek President and COO Chen Kuan-chou, Navid Shahriari steps into an expansive leadership portfolio designed to institutionalize foundry-grade manufacturing rigor within MediaTek's rapidly expanding data center and hyperscale AI accelerator divisions.
2. Executing a Dual CoWoS–EMIB Strategy
A. The Multi-Die Packaging Bottleneck in AI ASICs
Modern hyperscale AI accelerators—such as custom ASIC chips engineered for major cloud providers like Google—require massive arrays of High-Bandwidth Memory (HBM) stacks coupled with sprawling compute dies. Because monolithic die scaling is constrained by reticle limits and thermal density, advanced 2.5D packaging has become the primary battleground for delivery timelines.
B. Bridging TSMC and Intel Foundry Ecosystems
By combining Shahriari's mastery over Intel’s packaging innovations (such as EMIB and bridge-based die interconnects) with former TSMC R&D executive Douglas Yu's deep expertise in CoWoS architectures, MediaTek is uniquely positioned to adopt a flexible, dual-foundry packaging strategy. This dual-sourcing capability mitigates industry-wide capacity constraints and allows MediaTek to tailor packaging topologies precisely to customer performance requirements.
| Packaging Dimension | Traditional Fabless Approach | MediaTek’s Dual-Veteran Strategy |
|---|---|---|
| Foundry Dependency | Single-source reliance (e.g., TSMC CoWoS capacity allocations) | Diversified multi-foundry packaging pipeline (CoWoS & EMIB integration) |
| Interconnect Topology | Standard interposer designs with fixed pitch limitations | Advanced bridge-die embedding and high-density thermal management |
| Data Center Scaling | Incremental generation rollouts tied to single vendor roadmaps | Rapid custom ASIC execution targeting multibillion-dollar AI revenue |
| Executive Pedigree | General product management and standard foundry interface | Direct leadership from former Intel and TSMC packaging executives |
Architectural Takeaways & Industry Outlook
Navid Shahriari’s transition from Intel to MediaTek marks a watershed moment for the fabless semiconductor landscape. As MediaTek targets a massive expansion in custom AI accelerator ASICs—projected to capture significant market share and multi-billion-dollar revenues—mastery over advanced packaging has become the ultimate differentiator.
By onboarding top-tier foundry packaging veterans from both Intel and TSMC, MediaTek is transforming from a mobile-first designer into an elite powerhouse for data center AI silicon. This technical depth ensures that next-generation custom ASICs will feature optimized thermal profiles, superior multi-die integration, and robust supply chain security.